TSMC can’t keep up with demand for its CoWoS advanced packaging, pushing some AI chip orders to Intel and Taiwanese packaging firms. As first reported by Wccftech, customers unable to secure enough CoWoS capacity are evaluating Intel’s EMIB technology and services from ASE, SPIL, Powertech, and KYEC. The shift could alter the competitive landscape for data-center accelerators and impact IT procurement timelines.

The bottleneck isn’t silicon — it’s how chips are stitched together

Advanced packaging has become the unsung hero of modern AI accelerators. TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) technology bonds large logic dies with stacks of high-bandwidth memory (HBM) inside a single package. It’s what makes Nvidia’s H200 and Blackwell GPUs, AMD’s Instinct MI300X, and custom cloud ASICs possible at scale.

But TSMC’s CoWoS capacity is stretched thin. At the company’s June 2026 shareholders meeting, CEO C.C. Wei admitted it would “take a long time” to satisfy customer demand. TrendForce reports that the CoWoS supply-demand gap could narrow from roughly 20% to 10% by the end of 2026 as new production lines come online — but for now, the crunch is real.

That crunch has opened the door for Intel. Its EMIB (Embedded Multi-Die Interconnect Bridge) technology uses tiny silicon bridges instead of a full interposer, offering a different approach to stitching chiplets together. Intel has been aggressively courting foundry customers for advanced packaging, and while no official deal has been confirmed, Wccftech repeats earlier speculation that Nvidia might send future Feynman-generation GPU packaging orders to Intel. More likely in the short term: custom accelerators and cloud-provider ASICs that can design around EMIB from the start.

Meanwhile, Taiwanese OSATs (outsourced semiconductor assembly and test firms) — including ASE, SPIL, Powertech, and KYEC — are also picking up overflow orders. They don’t replicate TSMC’s integrated fab-to-packaging flow, but they can handle assembly, testing, and alternative 2.5D integration for customers willing to qualify them.

What this means for you

The impact depends on your role in the tech stack. Here’s the breakdown:

Enterprise IT buyers and datacenter planners

If you’re procuring AI servers, the CoWoS shortage isn’t just TSMC’s problem — it’s yours. Lead times for GPU-accelerated systems may stretch further, and prices could remain elevated. Now, packaging allocation and vendor qualification replace simple GPU model availability as the gating factor.

Practical steps:
- Ask server vendors explicitly about their packaging supply chain, not just chip model roadmaps.
- Diversify your sourcing: consider AMD MI-series accelerators alongside Nvidia; their packaging choices differ.
- Account for the possibility of last-minute supplier swaps. A design that starts on CoWoS might end up on EMIB or an OSAT flow, potentially affecting system validation — build that into your evaluation timeline.

Cloud users and SaaS developers

If you rent AI instances from AWS, Azure, or GCP, you’re insulated from the immediate packaging scramble. But a sustained bottleneck can delay the rollout of new instance types. For example, if Nvidia shifts high-end packaging to Intel, that could require requalification and slow time-to-cloud.

What to watch: Cloud providers’ launch cadence for next-gen AI instances. If timelines slip, explore whether current-generation instances can meet your needs a bit longer, or consider alternative cloud AI services that abstract the hardware.

Windows PC users and power users

This is a data-center story, not a consumer one. The CoWoS shortage won’t affect the availability of gaming GPUs or laptop CPUs. Even enthusiast parts like the RTX 5090 don’t use advanced 2.5D packaging at the scale of data-center chips. Your next DIY build is safe.

Developers building on-premises AI

If you’re integrating accelerators into on-premises infrastructure, treat packaging as a technical criterion. Designs that rely on EMIB may have different power, thermal, or verification characteristics than CoWoS-based equivalents. Engage early with silicon vendors to understand the implications for your workload.

How we got here

The advanced packaging crunch didn’t appear overnight. TSMC pioneered CoWoS over a decade ago, and its early lead became a moat as AI demand exploded. Nvidia’s A100, H100, and now Blackwell GPUs all depend on CoWoS-S or CoWoS-L variants. When the generative AI boom hit in 2023, orders surged beyond anyone’s forecast.

TSMC’s response has been a construction blitz: five packaging plants in Taiwan are already running, with more on the way in Taoyuan, Miaoli, and eventually two facilities in Arizona as part of the company’s 12-fab expansion plan. But these projects take years to bring online, and even when brick-and-mortar is ready, ramping yields on advanced packaging is slow.

Intel saw the opportunity. After opening its foundry to external customers, it made EMIB and Foveros centerpieces of its pitch. EMIB’s key advantage: it doesn’t need a large, expensive silicon interposer, which can lower cost and improve yields for very large packages. Intel has also capitalized on Washington’s desire for domestic advanced packaging, securing CHIPS Act funding to expand facilities in New Mexico and beyond.

Taiwan’s OSATs, meanwhile, have long competed on cost and flexibility for simpler packages. The CoWoS squeeze gives them a chance to climb the value chain into 2.5D integration, though doing so requires investment and customer trust.

The result is a fragmented packaging landscape. A chip that was once a CoWoS design might now have paths through EMIB or OSAT flows — but each path requires unique engineering, qualification, and HBM supply arrangements. It’s not a simple drop-in replacement.

What to do now

If your organization relies on AI infrastructure, start the conversation now. Here’s a checklist:

  • Reach out to hardware vendors: Ask for clarity on packaging assumptions. For example, is the quoted lead time for a server based on CoWoS, EMIB, or something else? What happens if the supplier changes?
  • Evaluate multi-source options: Don’t pin your roadmap on a single accelerator family. AMD’s upcoming Instinct MI400 and MI500 are expected to use TSMC’s advanced packaging, but AMD may also qualify alternative flows. Intel’s Gaudi and Falcon Shores lines natively use EMIB. A multi-vendor approach hedges packaging risk.
  • Monitor cloud roadmaps closely: If you’re a cloud buyer, watch for subtle delays in instance announcements. That may be your cue to lock in current capacity.
  • Accept slightly longer planning cycles: Treat AI server procurement more like a custom silicon project: plan on 12–18 months from purchase order to deployment, rather than the 6–9 months of a standard rack.

Outlook

TSMC’s CoWoS capacity will expand. TrendForce’s forecast of a narrowing gap from 20% to 10% by year-end 2026 suggests the worst may be behind us by early 2027. But AI demand is a moving target. As model sizes grow and inference workloads demand more HBM, packaging will remain a critical path.

Intel’s EMIB is the wildcard. If it secures a marquee win — say, packaging for a major Nvidia GPU or a high-volume AWS Trainium chip — it would validate EMIB as a true CoWoS alternative and force the industry to rethink sourcing. The rumored Nvidia Feynman deal remains unconfirmed, but even a smaller custom ASIC win could tip the scales.

For now, the CoWoS bottleneck is a reminder that the semiconductor supply chain has new choke points. Silicon fabrication gets the headlines, but packaging and assembly increasingly determine what gets delivered, and when.