Kuala Lumpur, Malaysia — On June 12, 2026, CADFEM APAC and SilTerra Malaysia Sdn. Bhd. put pen to paper on a memorandum of understanding that promises to bridge the gap between sophisticated engineering simulation and the gritty reality of semiconductor manufacturing. The partnership, announced at a ceremony in Kuala Lumpur, aims to infuse every stage of chip design and fabrication with multiphysics simulation, compressing development cycles and elevating the performance, efficiency, and reliability of silicon destined for Windows‑powered devices and beyond.

For users of Windows laptops, tablets, and edge computing hardware, this collaboration signals a future where next‑generation processors arrive faster, run cooler, and pack more intelligence per square millimeter. By marrying CADFEM’s deep expertise in ANSYS‑powered simulation with SilTerra’s proven 200‑mm (8‑inch) wafer‑fabrication capabilities, the two companies intend to tackle the escalating complexity of modern semiconductor nodes, advanced packaging, and heterogeneous integration—all of which demand a simulation‑first mindset.

The MoU: What It Entails

The memorandum of understanding outlines a multi‑year framework under which CADFEM APAC will provide simulation software, methodology consulting, and training to SilTerra’s design and process engineering teams. The goal is to embed simulation‑driven engineering at the very inception of new technology platforms, rather than treating it as a late‑stage verification step. Key areas of collaboration include:

  • Technology‑CAD (TCAD) and process simulation for optimizing doping profiles, lithography, and etch uniformity on SilTerra’s 0.13 µm to 0.11 µm nodes—and for future roadmap extensions into sub‑100 nm geometries.
  • Multiphysics co‑simulation of electrical, thermal, and mechanical behavior, crucial for power management ICs, MEMS sensors, and advanced RF devices where second‑order effects can make or break product yields.
  • Chip‑package‑system (CPS) simulation for 2.5D and 3D advanced packaging, including silicon interposers and fan‑out wafer‑level packaging (FOWLP), which SilTerra has been ramping up for AI accelerators and high‑bandwidth memory.
  • Design‑for‑manufacturability (DFM) loops that feed simulated manufacturability data back to chip designers early enough to avoid costly respins.

Neither company disclosed the financial terms, but sources close to the matter describe the MoU as a landmark step toward transforming SilTerra from a pure‑play foundry into a simulation‑enabled design‑support powerhouse.

CADFEM and SilTerra: A Closer Look

CADFEM APAC is the regional arm of CADFEM International, an elite ANSYS channel partner that has been delivering simulation solutions across the Asia‑Pacific for over three decades. Headquartered in Singapore, with offices in Malaysia, India, and Indonesia, CADFEM APAC specializes in structural, fluid, electromagnetic, and system simulation, serving industries from automotive to high‑tech electronics. Its consultants regularly assist fabless chip designers, foundries, and OSATs (outsourced semiconductor assembly and test) in deploying virtual prototyping to slash physical testing costs.

SilTerra Malaysia Sdn. Bhd. operates one of the region’s most versatile 200‑mm wafer fabs in Kulim Hi‑Tech Park, Kedah. Originally established with government backing, SilTerra was acquired by Dagang NeXchange Berhad (DNeX) and strategic investors in 2021, and has since pivoted from commodity CMOS logic to higher‑value specialty technologies. Today, its portfolio includes:

  • High‑voltage BCD (Bipolar‑CMOS‑DMOS) for power management and automotive gate drivers.
  • MEMS and sensor platforms for accelerometers, pressure sensors, and micro‑mirrors.
  • Photonics and silicon‑based PCR (polymerase chain reaction) chips for point‑of‑care diagnostics.
  • Advanced packaging interposers and via‑middle TSV (through‑silicon‑via) technology for chiplet integration.

With a monthly capacity exceeding 40,000 wafer starts, SilTerra supplies chips that quietly underpin millions of Windows‑powered notebooks, IoT endpoints, and industrial systems globally. Its customers include integrated device manufacturers, fabless startups, and tier‑one system houses that demand rapid prototyping and reliable volume production.

Simulation‑Driven Engineering in Semiconductor Design

Semiconductor simulation is not new, but its role is shifting from isolated niche analyses to a continuous thread woven through the entire product lifecycle. Historically, a chip designer would run static timing analysis or spice simulations on schematics; a process engineer would separately tweak furnace recipes based on physical trial wafers. The CADFEM‑SilTerra MoU envisions a unified workflow where the same multiphysics models inform architecture decisions, layout, mask synthesis, and process tuning concurrently.

Why now? Three trends make simulation indispensable:

  1. Extreme complexity of modern ICs. Even on mature 200‑mm nodes, integrating power FETs, logic, MEMS, and RF circuits on a single die demands co‑optimization of dozens of interdependent parameters. Minor drifts in gate oxide thickness can cascade into parametric yield losses.
  2. Cost of physical prototyping. A mask set for a 130 nm BCD process can exceed $1 million, and every design‑of‑experiments lot adds weeks. Simulation allows engineers to explore a far wider design space virtually before committing to silicon.
  3. Advanced packaging heterogeneity. In a chiplet‑based design, the interaction between dies, interposer, redistribution layers, and micro‑bumps introduces mechanical stress hotspots and thermal crosstalk that are impossible to intuit without full‑system multiphysics simulation.

CADFEM’s ANSYS‑based toolchain brings validated physics engines—from semiconductor‑level simulation using ANSYS RedHawk‑SC for power integrity, to Icepak for thermal analysis, to Mechanical for warpage and stress. By coupling these tools with SilTerra’s proprietary process design kits (PDKs), engineers can predict not just if a circuit will function, but how well it will yield in a given fab line.

Why This Matters for Windows Hardware

Windows 11 and the pending Windows 12 ecosystem are pushing hardware requirements higher: neural processing units (NPUs) for on‑device AI, always‑connected standby with ultra‑low power draw, and seamless transitions between performance and efficiency cores. Meeting these demands places enormous strain on the semiconductor supply chain.

Performance and power efficiency. Whether it’s an Intel Meteor Lake successor, an AMD Ryzen APU, or a Qualcomm Snapdragon X Elite processor for Copilot+ PCs, all rely on advanced process nodes and sophisticated power management ICs (PMICs). SilTerra’s BCD technology—capable of integrating 200‑V power transistors alongside dense digital logic—cranks out the PMICs that regulate voltage rails inside Windows laptops. Simulation‑driven optimization of these PMICs can directly translate into longer battery life and quieter fan‑less designs, because parasitic capacitances and leakage currents are modeled and minimized before first silicon.

AI acceleration at the edge. Windows is increasingly embedding AI features: real‑time camera effects, voice clarity, and Copilot reasoning. Many of these workloads run on small, dedicated NPUs or microcontroller‑class devices fabricated on mature nodes to keep costs low. SilTerra’s MEMS and sensor platforms, combined with simulation‑verified ASICs, can yield low‑power sensor hubs that offload the main processor. For example, an intelligent presence detection chip—waking a laptop only when a user approaches—can be co‑simulated to balance sensitivity with false‑trigger immunity.

Advanced packaging for high‑performance computing. Gaming laptops and mobile workstations demand high‑bandwidth memory and GPU chiplets. SilTerra’s foray into TSV interposers and fan‑out packaging positions it as a potential supplier for multichip modules powering next‑gen Windows gaming devices. The MoU’s emphasis on chip‑package‑system simulation ensures that thermal and mechanical reliability issues are ironed out long before chips reach system builders, reducing the risk of throttling or premature failure.

Shorter time‑to‑market for Windows OEMs. PC makers like Dell, HP, and Lenovo typically work on 18‑month product cycles. Any delay in silicon delivery can ripple into missed holiday seasons or back‑to‑school launches. By shrinking the design‑to‑tapeout phase through virtual prototyping, SilTerra can give its fabless customers faster design turns, helping OEMs keep their Windows roadmaps on schedule.

The Malaysian Tech Ecosystem and Global Implications

Malaysia has long been a quiet giant in the global semiconductor ecosystem, contributing roughly 13% of worldwide chip testing and packaging. The government’s National Semiconductor Strategy, launched in 2024, aims to move the country up the value chain from assembly and test into front‑end design and intellectual property (IP) creation. The CADFEM‑SilTerra MoU fits squarely within this ambition, signaling that Malaysia can host not just volume production but also the sophisticated engineering simulation that steers Moore’s Law.

For CADFEM APAC, the deal cements its footprint in Malaysia’s expanding high‑tech sector. The company already runs simulation workshops for local universities and SMEs, and the SilTerra collaboration will likely spawn a pipeline of simulation‑literate engineers who can staff future fabs or design firms. SilTerra, meanwhile, gains a powerful differentiator in the fiercely competitive foundry landscape: a simulation‑backed “more than Moore” service that promises higher first‑pass yields and faster time‑to‑market for niche mixed‑signal and power products.

Regionally, the partnership could inspire similar tie‑ups across Southeast Asia, where foundries in Singapore, the Philippines, and Thailand are also seeking to modernize. As geopolitical shifts encourage “China+1” supply chain diversification, Malaysia’s neutral status and mature infrastructure make it a magnet for semiconductor investment, and simulation expertise only sweetens the proposition.

Challenges and the Road Ahead

While the MoU sets an ambitious direction, real execution will test both parties. Integrating multiphysics simulation into an existing production fab is not merely a software installation—it requires cultural change. Process engineers accustomed to empirical “recipe tweaking” must learn to trust virtual models, while simulation experts must adapt their tools to the gritty constraints of a 200‑mm fab still running decades‑old equipment alongside modern modules.

Data integration is another hurdle. Simulation tools feed on accurate material properties, equipment‑specific process parameters, and historical wafer‑probe data. SilTerra will need to curate and maintain a “golden” dataset that is continuously updated, requiring robust IT‑OT convergence. CADFEM’s consulting teams will likely spend months on‑site in Kulim, fine‑tuning models against actual production measurements before the simulation results become trustworthy enough to drive decisions.

There is also the question of scale. SilTerra’s specialty technologies are highly customized; each customer’s design may demand a unique simulation setup. Balancing bespoke services against the foundry’s need for standardized, high‑throughput manufacturing will be a delicate art. The MoU envisions creating “simulation IP blocks” that can be reused across multiple customer engagements, but building that library will take time.

Despite these challenges, the momentum is clear. Silicon complexity is not going to unwind itself, and simulation is the only lever left to manage it affordably. For the Windows ecosystem, a more agile and simulation‑driven SilTerra translates into a broader, more innovative supplier base for chips that power everything from Surface tablets to industrial IoT gateways.

What Comes Next

In the immediate term, the two companies will establish joint working groups focused on BCD device simulation and MEMS reliability. Pilot projects with selected key customers are expected to kick off by Q4 2026, with the first simulation‑optimized silicon tapeouts targeted for early 2027. Industry watchers will monitor whether the partnership can convert technological promise into tangible yield improvements and design‑cycle reductions.

Looking further out, the MoU could pave the way for a full‑blown Digital Twin of SilTerra’s fab—a virtual replica that simulates not just individual devices but the entire manufacturing flow, from wafer arrival to parametric test. Such a twin would enable real‑time process optimization and predictive maintenance, further compressing costs and raising quality. For Windows users, that means more reliable chips, longer‑lasting batteries, and the seamless AI experiences that Microsoft is betting its future on.

The CADFEM‑SilTerra collaboration is a quiet but consequential milestone. It underscores that the next chapter of semiconductor innovation will be written not in new lithography scanners alone, but in the digital threads of simulation that weave through design, manufacturing, and packaging. And as that thread tightens, Windows hardware will be among the first to feel the benefit.