Intel’s Fab 9 facility in Rio Rancho, New Mexico, has quietly become the company’s U.S. hub for advanced chip packaging — and this week Intel detailed just how far its capabilities have grown. In a July 29 newsroom post, the chipmaker revealed that its New Mexico operation can now build multi-chip packages surpassing eight times the standard reticle limit, with a road map to exceed twelve times by 2028. That scaling leap is set to shape the AI accelerators inside tomorrow’s cloud servers and, eventually, the AI-powered Windows PCs on your desk.

What’s changing inside Fab 9

To understand the news, you need to grasp one manufacturing constraint: the reticle limit. This is the maximum rectangular area — roughly 26 mm by 33 mm on today’s most advanced lithography tools — that can be patterned onto a silicon wafer in a single exposure. Traditional monolithic chips occupy one reticle field, but AI workloads demand far more transistors and memory than can fit in that space. The industry’s answer is to slice the design into smaller chiplets and connect them in a single package, effectively building a “silicon mosaic.”

Intel’s New Mexico operation is scaling that mosaic to unprecedented sizes. According to the company, its Fab 9 can now assemble packages that are eight times the area of a standard reticle, and it aims to reach more than twelve times by 2028. To make that happen, Intel relies on two complementary packaging technologies: Foveros and EMIB (Embedded Multi-Die Interconnect Bridge).

Foveros provides true 3D stacking, bonding compute, memory, and I/O tiles vertically atop a silicon interposer — what Intel’s principal engineer Chris Seibert likens to a “pizza crust” on which specialized toppings are mounted. “This is the tool that brings in a ‘pizza crust’, or silicon wafer, and whatever ‘pizza toppings’ or specialized chiplets you want, we feed into the other side of this machine, and it attaches them to the top of that ‘crust’,” Seibert explains. After a bake step, the stack is filled with epoxy and diced into individual packages.

EMIB, by contrast, tackles horizontal connections. Instead of a large, expensive interposer spanning the entire package, EMIB embeds tiny silicon bridges only where chips need to talk directly at high speed. This cuts cost while preserving bandwidth between neighboring dies.

The newest piece of the puzzle is EMIB-T, which Intel says adds through‑silicon vias (TSVs) to the bridge itself, allowing power to be delivered vertically through the bridge instead of routed around it. That may sound like an incremental tweak, but in AI accelerators where hundreds of watts pour into a palm-sized substrate, direct power pathways improve efficiency, reduce signal noise, and free up space for more high-bandwidth memory (HBM) stacks. Intel expects EMIB‑T to enter higher-volume customer production in the second half of 2026.

Equally important is the commercial framing: Intel is offering this packaging as a foundry service, not just for its own chips. “Some of the customers are coming to us first for advanced packaging,” says Katie Prouty, manager of Fab 9. “When we’re successful delivering to those customers, they’ll continue to grow their trust and faith in Intel as a foundry.” That’s a significant pivot — packaging, once a back-end afterthought, is becoming a primary reason designers choose a manufacturing partner.

Why this matters for your Windows machine

For everyday Windows users, advanced packaging is invisible — but it increasingly defines what your laptop or desktop can do. Microsoft’s Copilot+ PCs, which run AI models locally, are the first wave of devices that will rely on heterogeneous chiplet designs. Qualcomm’s Snapdragon X Elite, AMD’s Ryzen AI 300 series, and Intel’s own Lunar Lake processors all use some form of advanced packaging to combine CPU cores, GPU tiles, neural processing units (NPU), and memory controllers on a single substrate. Intel’s Fab 9 innovations, particularly Foveros stacking and EMIB‑T power delivery, will filter into the next generation of these chips, expected in late 2026 and 2027.

The practical upshot: thinner, cooler-running laptops that can handle demanding AI tasks — real-time language translation, video background blur, on-device image generation — without draining the battery. Because Foveros allows power-hungry circuits to be built on efficient process nodes while high-performance logic uses leading-edge transistors, the overall package sips energy more intelligently. Intel’s own data shows that Foveros can help laptop batteries last longer, and edge devices fit into tighter spaces without sacrificing performance.

For power users and creators, the benefits are even more tangible. Graphics-intensive workloads, video editing, and local AI training benefit from huge memory bandwidth. EMIB‑T’s ability to support more HBM stacks directly impacts 3D rendering speed and the responsiveness of AI-assisted tools in Adobe Creative Suite or DaVinci Resolve. If you’re building a workstation today, you’ll likely see these packaging advances in Intel’s next-gen Xeon W or future Arc Pro GPUs.

IT professionals and data-center managers should care because the cloud services you depend on — Microsoft Azure AI, Microsoft 365 Copilot on the server side, and any SaaS that increasingly leans on AI inference — will be powered by accelerators built with these packaging technologies. Intel’s Gaudi AI accelerators and future Falcon Shores products will be assembled in New Mexico, aiming to compete with Nvidia’s dominant H200 and B200 units. Crucially, having this capacity on U.S. soil reduces geopolitical supply-chain risk; if you’re a CIO worried about Taiwan strait disruptions, Intel’s domestic packaging capability is a meaningful differentiator when selecting cloud or on-premise AI hardware.

How we got to the “silicon mosaic”

The journey from single-chip to system-of-chips has been decades in the making. Moore’s Law scaling of transistor density continues, but the economics of building ever-larger monolithic dies have broken down. Yields plummet, and physical limits — memory bandwidth walls, power delivery, heat dissipation — force a modular approach. AMD pioneered the concept in PCs with its Ryzen “chiplet” architecture in 2017; Apple followed with the M1 Ultra’s “UltraFusion” bridge; Intel brought chiplets to data-center CPUs with Sapphire Rapids.

But AI workloads have supercharged this trend. Training and running models like GPT‑4 require thousands of compute cores, terabytes of memory bandwidth, and massively parallel interconnects. Packaging is now as critical as the transistor process itself. Intel’s Rio Rancho site has been quietly at the center of this shift. What began in 1980 as a 25‑employee, 6‑inch wafer fab is now a 2,700‑person operation working with 500 suppliers — a testament to how packaging has evolved from a simple assembly step into a supply-chain-intensive manufacturing discipline.

Intel’s foundry strategy, launched in 2021, turned its internal packaging prowess into a merchant offering, competing with TSMC’s CoWoS (Chip on Wafer on Substrate) technology. The July 2026 announcement marks a milestone: EMIB‑T and the reticle‑limit expansion are not merely engineering bullet points but tangible production milestones that Intel says are ready for customer orders. The company has previously highlighted that customers designing AI accelerators are “thinking very carefully about what’s going to be needed to run AI workloads at scale,” and the New Mexico expansion is the factory manifestation of that thinking.

What to do now

For most Windows users, the answer is simple: you don’t need to take any immediate action. But if you’re planning a major hardware refresh, consider waiting until late 2026 or early 2027, when the first laptops and desktops with chips packaged using these latest New Mexico techniques appear. Those devices will likely offer a meaningful leap in AI performance and battery life compared to today’s best Copilot+ PCs.

Developers building on‑device AI applications using Windows Copilot Runtime, ONNX, or WebNN should start anticipating a more aggressively heterogeneous hardware environment. Chiplet‑based SoCs will mix compute tiles from different vendors and process nodes, potentially requiring runtime optimizations to distribute workloads across diverse cores. Familiarizing yourself with Intel’s oneAPI and Microsoft’s DirectML abstractions will pay off as these platforms mature.

For IT decision‑makers, Intel’s domestic advanced-packaging capability deserves a spot in your risk-assessment matrix. If your organization relies on custom ASICs or AI accelerators sourced from Asian foundries, Intel’s New Mexico site offers a geopolitically safer alternative for future designs. It’s also worth noting that Intel Foundry’s “package‑first” sales pitch — where customers choose packaging before the silicon process — could streamline development of specialized AI hardware, potentially shortening lead times from concept to deployment. Start conversations with your hardware vendors about whether Intel’s packaging services could fit your 2027–2028 infrastructure plans.

What to keep an eye on

The next 12 months will test Intel’s execution. Volume ramps of EMIB‑T are scheduled for the second half of 2026, but Intel has a history of manufacturing delays. Watch for concrete customer announcements — names like Microsoft, Amazon, or even a major GPU designer — that would validate the technology’s appeal beyond Intel’s own products.

Equally important is how competitors respond. TSMC is investing heavily in its own advanced packaging (CoWoS‑L, SoIC), and Samsung has been gaining ground. If TSMC matches or exceeds Intel’s reticle‑limit scaling, the window of differentiation may narrow. But for now, Intel’s Fab 9 in New Mexico has positioned itself at the bleeding edge of AI chip assembly. The silicon mosaics coming out of that desert plant will, within a few years, power the AI experiences you encounter daily — whether you’re aware of them or not.